module GateGen (
  input clk_50M,
  input rstn,
  output reg gate,
  output reg send_en
);
  

// 50ms秒等待，2s门限，50ms
localparam cnter_MAX      = 32'd105_000_000;
localparam cnter_gate_pos = 32'd002_500_000;
localparam cnter_gate_neg = 32'd102_500_000;
localparam cnter_senden   = cnter_MAX;

reg [31:0] cnter;

always @(posedge clk_50M, negedge rstn) begin
  if(!rstn) begin
    cnter <= 32'd0;
  end
  else if(cnter < cnter_MAX - 1) begin
    cnter <= cnter + 32'd1;
  end
  else begin
    cnter <= 32'd0;
  end
end


always @(posedge clk_50M, negedge rstn) begin
  if(!rstn) begin
    gate <= 1'b0;
  end
  else if(cnter < cnter_gate_pos - 1) begin
    gate <= 1'b0;
  end
  else if(cnter < cnter_gate_neg -1) begin
    gate <= 1'b1;
  end
  else begin
    gate <= 1'b0;
  end
end


always @(posedge clk_50M, negedge rstn) begin
  if(!rstn)
    send_en <= 1'd0;
  else if(cnter == cnter_senden - 10)
    send_en <= 1'd1;
  else
    send_en <= 1'd0;
end


endmodule